1. Field of Invention
The present invention relates to an integrated circuit. More particularly, the present invention relates to a clock cycle compensator and the method thereof.
2. Description of Related Art
Along with the manufacturing process scaling down in recently years, the environmental degradation becomes an issue on integrated circuits. For example, negative bias temperature instability (NBTI) degradation leads to a variation on a threshold voltage of the P-type metal-oxide-semiconductor field-effect transistor (MOSFET), and the variation affects a stability and a performance of an integrated circuit. For example, as the NBTI degradation impacts on a clock generation circuit in a dynamic random access memory (DRAM), a duty cycle of a clock signal generated from the clock generation circuit may be shifted. Further, in certain cases, the NBTI degradation may causes a failure in the DRAM.
Referring to FIG. 1, the effect of the NBTI degradation on a system clock signal is schematically shown. At time of beginning (i.e., timing axis, Time 0), the original effective in-system operational duty cycle range 100, EISODCR0, is denoted as EISODCR0=DC0±DCR, where the DC0 is the intrinsic duty cycle center point of the system clock signal and ±DCR is range of the duty cycle of the system clock signal. At time x, the time after the NBTI degradation, the corresponding effective in-system operational duty cycle range 120, EISODCRX, is denoted as EISODCRX=DC0±DCR±DCDX, where ±DCDX is the time shifted by the NBTI degradation. In other words, the NBTI degradation effectively shifts the intrinsic duty cycle by DCDX, which may cause certain potential clocking issues.
Therefore, a heretofore-unaddressed need exists for compensating the NBTI degradation to address the aforementioned deficiencies and inadequacies.